The following disclosure relates to semiconductor devices, and more particularly to a lateral double-diffused MOSFET (LDMOS) device.
Voltage regulators, such as DC to DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC to DC converters are particularly needed for battery management in low power devices, such as laptop notebooks and cellular phones. Switching voltage regulators (or simply “switching regulators”) are known to be an efficient type of DC-to-DC converter. A switching regulator generates an output voltage by converting an input DC voltage into a high frequency voltage, and filtering the high frequency input voltage to generate the output DC voltage. Specifically, the switching regulator includes a switch for alternately coupling and decoupling an input DC voltage source, such as a battery, to a load, such as an integrated circuit. An output filter, typically including an inductor and a capacitor, is coupled between the input voltage source and the load to filter the output of the switch and thus provide the output DC voltage. A controller, such as a pulse width modulator or a pulse frequency modulator, controls the switch to maintain a substantially constant output DC voltage.
Double-diffused drain (DDD) CMOS devices are commonly employed in switching regulators. DDD devices achieve high voltage tolerance through the introduction of a thick gate oxide (e.g., approximately 75 Angstroms for 3.3V applications and approximately 350 Angstroms for 12V applications) and a resistive implant at the drain. A voltage rating of a DDD device is typically determined by both the gate length and the spacing between the drain contact and the gate; thus establishing a trade-off between voltage rating and device performance.
FIG. 1A shows a conventional DDD CMOS device 100 on a p-type substrate 102. DDD CMOS device 100 includes a drain region 104 with an n-doped n+ region 106, and an n-doped deep drain (NDD) 108. Additionally, DDD CMOS device 100 includes a source region 112 and a single gate 114. Source region 112 includes an n-doped n+ region 116, and an p-doped p+ region 118. Gate 114 includes a conductive layer 120 (e.g., a polysilicon layer) and a thick oxide layer 122.
As shown in FIG. 1A, n+ region 106 can be self-aligned with respect to gate 114—i.e., n+ region 106 can be implanted into p-type substrate 102 after formation of gate 114 (during fabrication of DDD CMOS device 100). However, when n+ region 106 is self-aligned with respect to gate 114, n+ region 106 cannot have an offset (or spacing) from gate 114. Alternatively, n+ region 106 can have a predetermined offset (d) from gate 114 as shown in FIG. 1B. However, generally when n+ region 106 has an offset spacing (e.g., offset spacing (d)) with respect to gate 114, n+ region 106 is not typically self-aligned with respect to a gate (e.g., gate 114).